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| 1 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver june 2004 2004 integrated device technology, inc. dsc - 6502/14 c industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. features: ? 2.5 v dd ? 6 pairs of outputs ? low skew: 100ps all outputs at same interface level, 250ps all outputs at different interface levels ? selectable positive or negative edge synchronization ? tolerant of spread spectrum input clock ? synchronous output enable ? selectable inputs ? input frequency: 4.17mhz to 250mhz ? output frequency: 12.5mhz to 250mhz ? internal non-volatile eeprom ? jtag or i 2 c bus serial interface for programming ? hot insertable and over-voltage tolerant inputs ? feedback divide selection with multiply ratios of (1-6, 8, 10, 12) ? selectable hstl, ehstl, 1.8v/2.5v lvttl, or lvepecl input interface ? selectable hstl, ehstl, or 1.8v/2.5v lvttl output interface for each output bank ? selectable differential or single-ended inputs and six differen- tial outputs ? pll bypass for dc testing ? external differential feedback, internal loop filter ? low jitter: <75ps cycle-to-cycle, all outputs at same interface level: <100ps cycle-to-cycle all outputs at different interface levels ? power-down mode ? lock indicator ? available in vfqfpn package idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver description: the idt5t9821 is a 2.5v pll differential clock driver intended for high performance computing and data-communications applications. the idt5t9821 has six differential outputs in six banks, including a dedicated differential feedback. the redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent. the clock driver can be configured through the use of jtag/i 2 c program- ming. an internal eeprom will allow the user to save and restore the configuration of the device. the feedback bank allows divide-by-functionality from 1 to 12 through the use of jtag or i 2 c programming. this provides the user with frequency multiplication 1 to 12 without using divided outputs for feedback. each output bank also allows for a divide-by functionality of 2 or 4. the idt5t9821 features a user-selectable, single-ended or differential input to six differential outputs. the differential clock driver also acts as a translator from a differential hstl, ehstl, 1.8v/2.5v lvttl, lvepecl, or single-ended 1.8v/2.5v lvttl input to hstl, ehstl, or 1.8v/2.5v lvttl outputs. each output bank can be individually configured to be either hstl, ehstl, 2.5v lvttl, or 1.8v lvttl, including the feedback bank. also, each clock input can be individually configured to accept 2.5v lvttl, 1.8v lvttl, or differential signals. the outputs can be synchronously enabled/disabled. the differential outputs can be synchronously enabled/disabled. furthermore, all the outputs can be synchronized with the positive edge of the ref clock input. or the negative edge of ref.
2 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver 0 1 pll omode 1soe 1 q 1 q divide select v dd q1 2soe 2 q 2 q divide select v dd q2 3soe 3 q 3 q divide select v dd q3 4soe 4 q 4 q divide select v dd q4 5soe 5 q 5 q divide select v dd q5 qfb qfb divide select v dd qfb jtag/i2c programming selection and control logic (tdo) (addr1) tdo/addr1 tms/addr0 tclk/sclk tdi/sda trst/sel eeprom pd fb fb/v ref 2 ref0 ref0/v ref 0 ref1 ref1/v ref 1 ref_sel pll_en 0 1 /n lock( ) functional block diagram 3 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver pin configuration vfqfpn top view v d d v d d q 1 v d d v d d l o c k 1 q 1 s o e t d o / a d d r 1 t m s / a d d r 0 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 v d d q 1 2 q 2 s o e v d d q 2 v d d q 2 2 q 5 8 5 7 5 6 5 5 5 4 5 3 5 2 1 q v d d 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 v d d q f b p d p l l _ e n q f b v d d v d d q f b q f b v d d 1 8 1 9 v d d v d d 2 8 2 9 3 0 3 1 3 2 3 3 3 4 5 q v d d 5 q 5 s o e v d d q 5 v d d q 5 v d d 3soe omode v dd q3 v dd q3 3 q 51 50 49 48 47 46 45 44 43 42 3 q v dd v dd trst/sel v dd 4 q 4 q v dd q4 41 40 39 38 37 36 35 v dd q4 v dd 4soe ref_sel v dd ref 1 fb ref 1 /v ref1 ref 0 ref 0 /v ref0 2 3 4 5 6 7 1 fb/v ref2 8 9 10 v dd v dd nc nc nc nc 12 13 14 15 16 17 11 gnd tdi/sda tclk/sclk v dd v dd 4 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver note: 1. capacitance applies to all inputs except jtag/i 2 c signals, sel, addr0, and addr1. capacitance (t a = +25c, f = 1mhz, v in = 0v) parameter description min. typ. max. unit c in input capacitance 2.5 3 3.5 pf c out output capacitance ? 6.3 7 pf symbol description max unit v ddqn , v dd power supply voltage (2) ?0.5 to +3.6 v v i input voltage ?0.5 to +3.6 v v o output voltage ?0.5 to v ddq +0.5 v v ref reference voltage (3) ?0.5 to +3.6 v t j junction temperature 150 c t stg storage temperature ?65 to +165 c absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v ddqn and v dd internally operate independently. no power sequencing requirements need to be met. 3. not to exceed 3.6v. symbol description min. typ. max. unit t a ambient operating temperature ?40 +25 +85 c v dd (1) internal power supply voltage 2.3 2.5 2.7 v hstl output power supply voltage 1.4 1.5 1.6 v v ddqn (1) extended hstl and 1.8v lvttl output power supply voltage 1.65 1.8 1.95 v 2.5v lvttl output power supply voltage v dd v v t termination voltage v ddqn / 2 v recommended operating range note: 1. inputs are capable of translating the following interface standards. user can select between: single-ended 2.5v lvttl levels single-ended 1.8v lvttl levels or differential 2.5v/1.8v lvttl levels differential hstl and ehstl levels differential lvepecl levels pin description symbol i/o type description ref [1:0] i adjustable (1) clock input. ref [1:0] is the "true" side of the differential clock input. if operating in single-ended mode, ref [1:0] is the clock input. ref [1:0] / i adjustable (1) complementary clock input. ref [1:0] /v ref [1:0] is the "complementary" side of ref [1:0] if the input is in differential mode. if operating v ref [1:0] in single-ended mode, ref [1:0] /v ref [1:0] is left floating. for single-ended operation in differential mode, ref [1:0] /v ref [1:0] should be set to the desired toggle voltage for ref [1:0] : 2.5v lvttl v ref = 1250mv (sstl2 compatible) 1.8v lvttl, ehstl v ref = 900mv hstl v ref = 750mv lvepecl v ref = 1082mv fb i adjustable (1) clock input. fb is the "true" side of the differential feedback clock input. if operating in single-ended mode, fb is the fee dback clock input. fb /v ref 2 i adjustable (1) complementary feedback clock input. fb /v ref 2 is the "complementary" side of fb if the input is in differential mode. if operating in single- ended mode, fb /v ref 2 is left floating. for single-ended operation in differential mode, fb /v ref 2 should be set to the desired toggle voltage for fb: 2.5v lvttl v ref = 1250mv (sstl2 compatible) 1.8v lvttl, ehstl v ref = 900mv hstl v ref = 750mv lvepecl v ref = 1082mv note: 1. all power supplies should operate in tandem. if v dd or v ddqn is at maximum, then v ddqn or v dd (respectively) should be at maximum, and vice-versa. 5 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver pin description, continued symbol i/o type description ref_sel i lvttl (1) reference clock select. when low, selects ref 0 and ref 0 /v ref 0. when high, selects ref 1 and ref 1 /v ref 1. nsoe i lvttl (1) synchronous output enable/disable. each outputs's enable/disable state can be controlled either with the nsoe pin or through jtag or i 2 c programming, corresponding bits 52 - 56. when the nsoe is high or the corresponding bit (52 - 56) is 1, the output will be synchronously disabled. when the nsoe is low and the corresponding bit (52 - 56) is 0, the output will be enabled. (see jtag/i 2 c serial configuration table.) qfb o adjustable (2) feedback clock output qfb o adjustable (2) complementary feedback clock output nq o adjustable (2) clock outputs nq o adjustable (2) complementary clock outputs pll_en i lvttl (1) pll enable/disable control. the pll's enable/disable state can be controlled either with the pll_en pin or through jtag or i 2 c programming, corresponding bit 57. when pll_en is high or the corresponding bit 57 is 1, the pll is disabled and ref [1:0] goes to all outputs. when pll_en is low and the corresponding bit 57 is 0, the pll will be active. pd i lvttl (1) power down control. when pd is low, the inputs are disabled and internal switching is stopped. the omode pin in conjunction with the corresponding bit 59 selects whether the outputs are gated low/high or tri-stated. when omode is high or bit 59 is 1, bit 58 determines the level at which the outputs stop. when bit 58 is 0/1, the nq and qfb are stopped in a high/low state, whi le the nq and qfb are stopped in a low/high state. when omode is low and bit 59 is 0, the outputs are tri-stated. set pd high for normal operation. (see jtag/i 2 c serial configuration table.) lock o lvttl pll lock indication signal. high indicates lock. low indicates that the pll is not locked and outputs may not be synchronized to the inputs. the output will be 2.5v lvttl. omode i lvttl (1) output disable control. used in conjunction with nsoe and pd . the outputs' disable state can be controlled either with the omode pin or through jtag or i 2 c programming, corresponding bit 59. when omode is high or the corresponding bit 59 is 1, the outputs' disable state will be gated and bit 58 will determine the level at which the outputs stop. when bit 58 is 0/1, the nq and qfb are stopped in a high/low state, while the nq and qfb are stopped in a low/high state. when omode is low and its corresponding bit 59 is 0, the outputs disable state will be the tri-state. (see jtag/i 2 c serial configurations tables.) trst /sel i/i lvttl/ trst - active low input to asynchronously reset the jtag boundary-scan circuit. lvttl (4,5) sel - select programming interface control for the dual-function pins. when high, the dual-function pins are set for jtag prog ramming. when low, the dual-function pins are set for i 2 c programming and the jtag interface is asynchronously placed in the test logic reset state. tdo/addr1 o/i lvttl/ tdo - serial data output pin for instructions as well as test and programming data. data is shifted in on the falling edge of tclk. the pin is tri-stated if data is not being shifted out of the device. addr1 - used to define a unique i 2 c address for this device. only for i 2 c programming. (see jtag/i 2 c serial interface description.) tms/addr0 i/i lvttl/ tms - input pin that provides the control signal to determine the transitions of the jtag tap controller state machine. transi tions within the state machine occur at the rising edge of tclk. therefore, tms must be set up before the rising edge of tclk. tms is eval uated on the rising edge of tclk. addr0 - used to define a unique i 2 c address for this device. only for i 2 c programming. (see jtag/i 2 c serial interface description.) tclk/sclk i/i lvttl/ tclk - the clock input to the jtag bst circuitry. sclk - serial clock for i 2 c programming tdi/sda i/i lvttl/ tdi - serial input pin for instructions as well as test and programming data. data is shifted in on the rising edge of tclk. sda - serial data (see jtag/i 2 c serial description table) v ddqn pwr power supply for each pair of outputs. when using 2.5v lvttl, 1.8v lvttl, hstl, or ehstl outputs, v ddqn should be set to its corresponding outputs (see front block diagram). when using 2.5v lvttl outputs, v ddqn should be connected to v dd. v dd pwr power supply for phase locked loop, lock output, inputs, and other internal circuitry gnd pwr ground 3-level (3,4,5) 3-level (3,4,5) lvttl (4,5) lvttl (4,5) notes: 1. pins listed as lvttl inputs can be configured to accept 1.8v or 2.5v signals through the use of the i 2 c/jtag programming, bit 61. (see jtag/i 2 c serial description.) 2. outputs are user selectable to drive 2.5v, 1.8v lvttl, ehstl, or hstl interface levels when used with the appropriate v ddqn voltage. 3. 3-level inputs are static inputs and must be tied to v dd or gnd or left floating. these inputs are not hot-insertable or over voltage tolerant. 4. the jtag (tdo, tms, tclk, and tdi) and i 2 c (addr1, addr0, sclk, and sda) signals share the same pins (dual-function pins) for which the trst /sel pin will select between the two programming interfaces. 5. jtag and i 2 c pins accept 2.5v signals. the jtag input pins (tms, tclk, tdi, trst ) will also accept 1.8v signals. 6 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver jtag/ i 2 c serial description bit description 95:62 reserved bits. set bits 95:62 to '0'. 61 input interface selection for control pins (ref_sel, pd , pll_en , omode nsoe ). when bit 61 is ?1?, the control pins are 2.5v lvttl. when bit 61 is ?0?, the control pins are 1.8v lvttl. 60 vco frequency range. when ?0?, range is 50mhz-125mhz. when ?1?, range is 100mhz-250mhz. 59 output?s disable state. see corresponding external pin omode for pin description table. 58 positive/negative edge control. when ?0?/?1?, the outputs are synchronized with the negative/positive edge of the reference clock. 57 pll enable/disable. see corresponding external pin pll_en in pin description table. (1) 56 output disable/enable for 1q/ 1q outputs. see corresponding external pin 1soe in pin description table. 55 output disable/enable for 2q/ 2q outputs. see corresponding external pin 2soe in pin description table. 54 output disable/enable for 3q/ 3q outputs. see corresponding external pin 3soe in pin description table. 53 output disable/enable for 4q/ 4q outputs. see corresponding external pin 4soe in pin description table. 52 output disable/enable for 5q/ 5q outputs. see corresponding external pin 5soe in pin description table. 51 fb divide-by-n selection 50 fb divide-by-n selection 49 fb divide-by-n selection 48 fb divide-by-n selection 47 output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on bank 1 46 output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on bank 1 45 output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on bank 2 44 output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on bank 2 43 output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on bank 3 42 output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on bank 3 41 output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on bank 4 40 output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on bank 4 39 output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on bank 5 38 output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on bank 5 37 fb output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on fb bank 36 fb output drive strength selection for 2.5v lvttl, 1.8v lvttl, or hstl/ehstl on fb bank 35 ref0 input interface selection for 2.5v lvttl, 1.8v lvttl, or differential 34 ref0 input interface selection for 2.5v lvttl, 1.8v lvttl, or differential 33 ref1 input interface selection for 2.5v lvttl, 1.8v lvttl, or differential 32 ref1 input interface selection for 2.5v lvttl, 1.8v lvttl, or differential 31 fb input interface selection for 2.5v lvttl, 1.8v lvttl, or differential 30 fb input interface selection for 2.5v lvttl, 1.8v lvttl, or differential 29 divide selection for bank 1 28 divide selection for bank 1 27 divide selection for bank 1 26 divide selection for bank 1 25 divide selection for bank 1 24 divide selection for bank 2 23 divide selection for bank 2 22 divide selection for bank 2 21 divide selection for bank 2 note: 1. only for eeprom operation; bit 57 must be set to 0 to enable the pll for proper eeprom operation. the eeprom access times ar e based on the vco frequency of the pll (refer to the eeprom operation section). 7 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver jtag/ i 2 c serial description, cont. bit description 20 divide selection for bank 2 19 divide selection for bank 3 18 divide selection for bank 3 17 divide selection for bank 3 16 divide selection for bank 3 15 divide selection for bank 3 14 divide selection for bank 4 13 divide selection for bank 4 12 divide selection for bank 4 11 divide selection for bank 4 10 divide selection for bank 4 9 divide selection for bank 5 8 divide selection for bank 5 7 divide selection for bank 5 6 divide selection for bank 5 5 divide selection for bank 5 4 divide selection for fb bank 3 divide selection for fb bank 2 divide selection for fb bank 1 divide selection for fb bank 0 divide selection for fb bank jtag/ i 2 c serial configurations: output enable/disable bit 59 (omode) bit 56-52 ( nsoe ) output x (x) 0 and (l) nor mal operation 0 and (l) 1 or (h) tri-sate 1 or (h) 1 or (h) gated (1) note : 1. omode and its corresponding bit 59 selects whether the outputs are gated low/ high or tri-stated. when omode is high or the corresponding bit 59 is 1, the outputs' disable state will be gated. bit 58 determines the level at which the outputs stop. when bit 58 is 0/ 1, the nq and qfb are stopped in a high/low state, while the nq and qfb are stopped in a low/high state. when omode is low and its corresponding bit 59 is 0, the outputs' disable state will be the tri-state. jtag/ i 2 c serial configurations: powerdown pd bit 59 (omode) output h x (x) normal operation l 0 and (l) tri-sate l 1 or (h) gated (1) note : 1. omode and its corresponding bit 59 selects whether the outputs are gated low/ high or tri-stated. when omode is high or the corresponding bit 59 is 1, the outputs' disable state will be gated. bit 58 determines the level at which the outputs stop. when bit 58 is 0/ 1, the nq and qfb are stopped in a high/low state, while the nq and qfb are stopped in a low/high state. when omode is low and its corresponding bit 59 is 0, the outputs' disable state will be the tri-state. jtag/ i 2 c serial configurations: clock input interface selec- tion (1) bit 31, 33, 35 bit 30, 32, 34 interface 0 0 differential (2) 0 1 2.5v lvttl 1 1 1.8v lvttl notes : 1. all other states that are undefined in the table will be reserved. 2. differential input interface for hstl/ehstl, lvepecl (2.5v), and 2.5v/1.8v lvttl. jtag/ i 2 c serial configurations: output drive strength selection (1) bit 37, 39, 41, bit 36, 38, 40, 43, 45, 47 42, 44, 46 interface 0 0 2.5v lvttl 0 1 1.8v lvttl 1 0 hstl/ehstl note : 1. all other states that are undefined in the table will be reserved. 8 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver jtag/ i 2 c serial configurations: skew or frequency select (1) bit 4, 9, 14, bit 3, 8, 13, bit 2, 7, 12, bit 1, 6, 11, bit 0, 5, 10, output skew 19, 24, 29 18, 23, 28 17, 22, 27 16, 21, 26 15, 20, 25 0 0 0 0 0 zero skew 1 0 0 0 0 inverted 1 0 0 0 1 divide-by-2 1 0 0 1 0 divide-by-4 note : 1. all other states that are undefined in the table will result in zero skew. jtag/ i 2 c serial configurations: fb divide-by-n (1) bit 51 bit 50 bit 49 bit 48 divide-by-n permitted output divide-by-n connected to fb and fb /vref2 (2) 0 0 0 0 1 1, 2, 4 0 0 0 1 2 1, 2 0010 3 1 0 0 1 1 4 1, 2 0 1 0 0 5 1, 2 0 1 0 1 6 1, 2 0110 8 1 011110 1 100012 1 notes : 1. all other states that are undefined in the table will be reserved. 2. permissible output division ratios connected to fb and fb /vref2. the frequencies of the ref[1:0] and ref [1:0]/vref[1:0] inputs will be fvco/n when the parts are configured for frequency multiplication by using an undivided output for fb and fb /vref2 and setting n (n = 1-6, 8, 10, 12). external differential feedback by providing a dedicated external differential feedback, the idt5t9821 gives users flexibility with regard to divide selection. the fb and fb / v ref2 signals are compared with the input ref [1:0] and ref [1:0] /v ref[1:0] signals at the phase detector in order to drive the vco. phase differ- ences cause the vco of the pll to adjust upwards or downwards accordingly. an internal loop filter moderates the response of the vco to the phase detector. the loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accu- rate responses to input frequency changes. input/output selection (1) input output (2) 2.5v lvttl se 2.5v lvttl, 1.8v lvttl se 1.8v lvttl, 2.5v lvttl dse hstl, 1.8v lvttl dse ehstl lvepecl dse ehstl dse hstl dse 2.5v lvttl dif 1.8v lvttl dif lvepecl dif ehstl dif hstl dif notes: 1. the input/output selection table describes the total possible combinations of input and output interfaces. single-ended (se) inputs in a single-ended mode require the ref [1:0] /v ref [1:0] and fb /v ref 2 pins to be left floating. differential single-ended (dse) is for single-ended operation in differential mode, requiring v ref [1:0] and v ref 2 . differential (dif) inputs are used only in differential mode. 2. for each output bank. master reset functionality the idt5t9821 performs a reset of the internal output divide circuitry when all five output banks are disabled by toggling the nsoe pins high. when one or more banks of outputs are enabled by toggling the nsoe low(if the corresponding nsoe programming bits are also set low), the divide circuitry starts again from a known state. in the case that the fb output is selected for divide-by-2 or divide-by-4, the fb output will stop toggling while all five nsoe pins and bits are low, and loss of lock will occur. 9 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver i 2 c serial interface control the i 2 c interface permits the configuration of the idt5t9821. the idt5t9821 is a read/write slave device meeting philips i 2 c bus specifications. the i 2 c bus is controlled by a master device that generates the serial clock sclk, controls bus access, and generates the start and stop conditions while the device works as a slave. both master and slave can operate as a transmitter and receiver but the master device determines which mode is activated. bus conditions data transfer on the bus can only be initiated when the bus is not busy. during data transfer, the data line (sda) must remain stable whenever the clock line (sclk) is high. changes in the data line while the clock line is high will be interpreted by the device as a start or stop condition. the following bus conditions are defined by the i 2 c bus protocol and are illustrated in figure 1. not busy both the data (sda) and clock (sclk) lines remain high to indicate the bus is not busy. start data transfer a high to low transition of the sda line while the sclk input is high indicates a start condition. all commands to the device must be preceded by a start condition. stop data transfer a low to high transition of the sda line while sclk is held high indicates a stop condition. all commands to the device must be followed by a stop condition. data valid the state of the sda line represents valid data if the sda line is stable for the duration of the high period of the sclk line after a start condition occurs. the data on the sda line must be changed only during the low period of the sclk signal. there is one clock pulse per data bit. each data transfer is initiated by a start condition and terminated with a stop condition. acknowledge when addressed, the receiving device is required to generate an acknowledge after each byte is received. the master device must generate an extra clock pulse to coincide with the acknowledge bit. the acknowledging device must pull the sda line low during the high period of the master acknowledge clock pulse. setup and hold times must be taken into account. address a0 is the read/write bit and is set to ?0? for writes and ?1? for reads. the addr0 and addr1 tri-level pins allow the last three bits of the 7-bit address to be defined by the user. write operation (see i 2 c interface definition for progwrite) to initiate a write operation (progwrite), the read/write bit is set to ?0?. during the write operation, the first two bytes transferred must be the device address followed by the command code. the internal programming registers of the device ignore these first two bytes. the subsequent bytes are the data bytes, which total twelve. all twelve data bytes must be written into the device during the write operation in order for the internal programming registers to be updated. if a stop condition is generated before the 12 th data byte, the internal programming registers will remain unchanged to prevent an invalid pll configuration. an acknowledge by the device between each byte must occur before the next byte is sent. after the transfer of the 12 th data byte, an acknowledge signal will be sent to the bus master after which it will generate a stop condition. once the stop condition has occurred, the internal programming registers of the device will be updated. read operation (see i 2 c interface definition for progread) to initiate a read operation (progread), the read/write bit is set to ?1?. during the read operation, there will be a total of fourteen data bytes returned following an acknowledge of the device address. the first two data bytes are the id byte and a reserved byte, in that order. the subsequent bytes are the same twelve data bytes that were written during the write operation. the read back can be terminated at any time by issuing a stop condition. i 2 c id byte id7 id6 id5 id4 id3 id2 id1 id0 00000101 i 2 c address a7 a6 a5 a4 a3 a2 a1 1101xx x addr1 addr0 a3 a2 a1 low low 0 0 0 low mid 0 0 1 low high 0 1 0 mid low 0 1 1 mid mid 1 0 0 mid high 1 0 1 high low 1 1 0 high mid 1 1 1 high high 1 1 0 jtag/ i 2 c serial configurations: vco frequency select bit 60 min. max. 0 50mhz 125mhz 1 100mhz 250mhz i 2 c bus operation the idt5t9821 i 2 c interface supports standard-mode (100khz) and fast- mode (400khz) data transfer rates. data is transferred in bytes in sequential order from the lowest to highest byte. after generating a start condition, the bus master broadcasts a 7-bit slave address followed by a read/write bit. 10 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver eeprom operation (see i 2 c interface definition for the eeprom instructions) the idt5t9821 can also store its configuration in internal eeprom. the contents of the device?s internal programming registers can be saved to the eeprom by issuing a save instruction (progsave) and can be loaded back to the internal programming registers by issuing a restore inst ruction (progrestore). to initiate a save or restore, only two bytes are transferred. the device address is issued with the read/write bit set to ?0? fo llowed by the appropriate command code. the save or restore instruction executes after the stop condition is received, during which time the idt5t9821 will not generate acknowledge bits. the device is ready to accept a new programming instruction once it acknowledges its 7-bit address. the time it takes for the save and restore instructions to complete depends on the pll oscillator frequency, f vco . the restore time, t restore , and the save time, t save , can be calculated as follows: t restore = 1.23x10 6 /f vco (ms) t save = 3.09x10 6 / f vco + 52 (ms) in order for the save and restore instructions to function properly, the idt5t9821 must not be in power-down mode ( pd must be high), and the pll must be enabled ( pll_en must be low and bit 57 = 0). on power-up of the idt5t9821 , an automatic restore is performed to load the eeprom contents into the internal programming regi sters. the auto-restore will not function properly if the device is in power-down mode ( pd must be high). the device?s auto-restore feature will function regardless of the state of the pll_en pin or bit 57. the idt5t9821 will be ready to accept a programming instruction once it acknowledges its 7-bit i 2 c address. the time it takes for the device to complete the auto-restore is approximately 3ms. programming notes once the idt5t9821 has been programmed either with a progwrite or progrestore instruction, the device will attempt to achieve p hase lock using the new pll configuration. if there is a valid ref and fb input clock connected to the device and it does not achieve lock, the user s hould issue a progread instruction to confirm that the pll configuration data is valid. on power-up and before the automatic progrestore instruction has completed, the internal programming registers will contain the value of ?0? for all bits 95:0. the pll will remain at the minimum frequency and will not achieve phase lock until after the automatic restore is completed. i f the outputs are enabled by the nsoe pins, the outputs will toggle at the minimum frequency. if the outputs are disabled by the nsoe pins and the omode pin is set high, the nq and qfb are stopped high, while nq and qfb are stopped low. sclk sda t su:start t su:stop stop data can change address or data valid t hd:start start sclk sda in t su:start t su:stop t hd:start t low t high t hd:data t su:data t buf t r t f t ovd t ovd sda out figure 1: i 2 c timing data 11 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver i 2 c interface definition progwrite s device address command code 7'b1101xxx 0 8'bxxxxxx00 aa m s b l s b m s b l s b data data byte 1 (bits 95 - 88) data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 data byte 9 data byte 10 data byte 11 data byte 12 (bits 7 - 0) a . . . a . . . a . . . a . . . a . . . a . . . a . . . a . . . a . . . a . . . a . . . a p s device address 7'b1101xxx 1 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 data byte 9 data byte 10 data byte 11 data byte 12 (bits 7 - 0) a . . . a . . . a . . . a . . . a . . . a . . . a . . . a . . . a . . . a . . . a . . . a p a id byte data byte 1 (bits 95 - 88) data byte 2 data byte 3 a . . . reserved byte a . . . 8'b00000101 r progread progsave s device address command code 7'b1101xxx 0 8'bxxxxxx01 a a p w progrestore s device address command code 7'b1101xxx 0 8'bxxxxxx10 a a p w id byte: part # id 5t9821 00000101 w 12 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver i 2 c bus dc characteristics symbol parameter conditions min typ max unit v ih input high level 0.7 * v dd v v il input low level 0.3 * v dd v v hys hysteresis of inputs 0.05 * v dd v i in input leakage current 1.0 a v ol output low voltage i ol = 3 ma 0.4 v i 2 c bus ac characteristics for standard mode symbol parameter min typ max unit f sclk serial clock frequency (sclk) 0 100 khz t buf bus free time between stop and start 4.7 s t su : start setup time, start 4.7 s t hd : start hold time, start 4 s t su : data setup time, data input (sda) 250 ns t hd : data hold time, data input (sda) (1) 0 s t ovd output data valid from clock 3.45 s c b capacitive load for each bus line 400 pf t r rise time, data and clock (sda, sclk) 1000 ns t f fall time, data and clock (sda, sclk) 300 ns t high high time, clock (sclk) 4 s t low low time, clock (sclk) 4.7 s t su : stop setup time, stop 4 s i 2 c bus ac characteristics for fast mode symbol parameter min typ max unit f sclk serial clock frequency (sclk) 0 400 khz t buf bus free time between stop and start 1.3 s t su : start setup time, start 0.6 s t hd : start hold time, start 0.6 s t su : data setup time, data input (sda) 100 ns t hd : data hold time, data input (sda) (1) 0 s t ovd output data valid from clock 0.9 s c b capacitive load for each bus line 400 pf t r rise time, data and clock (sda, sclk) 20 + 0.1 * c b 300 ns t f fall time, data and clock (sda, sclk) 20 + 0.1 * c b 300 ns t high high time, clock (sclk) 0.6 s t low low time, clock (sclk) 1.3 s t su : stop setup time, stop 0.6 s note: 1. a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the sclk signal) to bridge the undefined region of the falling edge of sclk. note: 1. a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the sclk signal) to bridge the undefined region of the falling edge of sclk. 13 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver jtag interface five additional pins (tdi, tdo, tms, tclk and trst ) are provided to support the jtag boundary scan interface. the idt5t9821 incorporates the necessary tap controller and modified pad cells to implement the jtag facility. note that idt provides appropriate boundary scan description language program files for these devices. test access port (tap) the tap interface is a general-purpose port that provides access to the internal of the processor. it consists of four input ports (tclk, tms, tdi, trst ) and one output port (tdo). the standard jtag interface consists of four basic elements: ? test access port (tap) ? tap controller ? instruction register (ir) ? data register port (dr) the following sections provide a brief description of each element. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). the tap controller the tap controller is a synchronous finite state machine that responds to tms and tclk signals to generate clock and control signals to the instruction and data registers for capture and update of data. boundary scan architecture tdo tdi tms tclk trst tap tap controller device id reg. boundary scan reg. bypass reg. mux instruction decode instruction register control signals clkdr, shiftdr updatedr clklr, shiftlr updatelr 14 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver notes: 1. five consecutive tclk cycles with tms = 1 will reset the tap. 2. tap controller must be reset before normal pll operations can begin. refer to the ieee standard test access port specification (ieee std.1149.1) for the full state diagram all state transitions within the tap controller occur at the rising edge of thetclk pulse. the tms signal level (0 or 1) determines the state progression that occurs on each tclk rising edge. the tap controller takes precedence over the pll and must be reset after power up of the device. see trst description for more details on tap controller reset. test-logic-reset all test logic is disabled in this controller state enabling the normal operation of the ic. the tap controller state machine is designed in such a way that, no matter what the initial state of the controller is, the test- logic-reset state can be entered by holding tms at high and pulsing tclk five times. this is the reason why the test reset ( trst ) pin is optional. run-test-idle in this controller state, the test logic in the ic is active only if certain instructions are present. for example, if an instruction activates the self test, then it will be executed when the controller enters this state. the test logic in the ic is idles otherwise. select-dr-scan this is a controller state where the decision to enter the data path or the select-ir-scan state is made. select-ir-scan this is a controller state where the decision to enter the instruction path is made. the controller can return to the test-logic-reset state otherwise. capture-ir in this controller state, the shift register bank in the instruction register parallel loads a pattern of fixed values on the rising edge of tclk. the last two significant bits are always required to be ?01?. shift-ir in this controller state, the instruction register gets connected between tdi and tdo, and the captured pattern gets shifted on each rising edge of tclk. the instruction available on the tdi pin is also shifted in to the instruction register. exit1-ir this is a controller state where a decision to enter either the pause- ir state or update-ir state is made. pause-ir this state is provided in order to allow the shifting of instruction register to be temporarily halted. exit2-dr this is a controller state where a decision to enter either the shift- ir state or update-ir state is made. update-ir in this controller state, the instruction in the instruction register is latched in to the latch bank of the instruction register on every falling edge of tclk. this instruction also becomes the current instruction once it is latched. capture-dr in this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of tclk. shift-dr, exit1-dr, pause-dr, exit2-dr and update-dr these controller states are similar to the shift-ir, exit1-ir, pause-ir, exit2-ir and update-ir states in the instruction path. tap controller state diagram test-logic reset run-test/ idle select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select- ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver the instruction register the instruction register allows an instruction to be shifted in serially into the processor at the rising edge of tclk. the instruction is used to select the test to be performed, or the test data register to be accessed, or both. the instruction shifted into the register is latched at the completion of the shifting process when the tap controller is at update- ir state. the instruction register must contain 4 bit instruction register-based cells which can hold instruction data. these mandatory cells are located nearest the serial outputs they are the least significant bits. test data register the test data register contains three test data registers: the bypass, the boundary scan register and device id register. these registers are connected in parallel between a common serial input and a common serial data output. the following sections provide a brief description of each element. for a complete description, refer to the ieee standard test access port specification (ieee std. 1149.1-1990). test bypass register the register is used to allow test data to flow through the device from tdi to tdo. it contains a single stage shift register for a minimum length in serial path. when the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of tclk when the tap controller is in the capture-dr state. the operation of the bypass register should not have any effect on the operation of the device in response to the bypass instruction. the boundary-scan register the boundary scan register allows serial data tdi be loaded in to or read out of the processor input/output ports. the boundary scan register is a part of the ieee 1149.1-1990 standard jtag implementation. the device identification register the device identification register is a read only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the tap in response to the idcode instruction. idt jedec id number is 0xb3. this translates to 0x33 when the parity is dropped in the 11-bit manufacturer id field. for the idt5t9821, the part number field is 0x3a7. jtag instruction register the instruction register allows instruction to be serially input into the device when the tap controller is in the shift-ir state. the instruction is decoded to perform the following: ? select test data registers that may operate while the instruction is current. the other test data registers should not interfere with chip operation and the selected data register. ir (3) ir (2) ir (1) ir (0) instruction function 0 0 0 0 extest select boundary scan register 0 0 0 1 sample/preload select boundary scan register 0 0 1 0 idcode select chip identification data register 0 0 1 1 reserved 0 1 0 0 progwrite writing to the volatile programming registers 0 1 0 1 progread reading from the volatile programming registers 0 1 1 0 progsave saving the contents of the volatile programming registers to the eeprom 0 1 1 1 progrestore loading the eeprom contents into the volatile programming registers 1 0 0 0 clamp jtag 1 0 0 1 highz jtag 1 0 1 x bypass select bypass register 1 1 x x bypass select bypass register jtag instruction register decoding ? define the serial test data register path that is used to shift data between tdi and tdo during data register scanning. the instruction register is a 4-bit field (i.e.ir3, ir2, ir1, ir0) to decode sixteen different possible instructions. instructions are decoded as follows. 31 (msb) 28 27 12 11 1 0(lsb) version (4 bits) part number manufacturer id 1 0x0 (16-bit) (11-bit) 0x33 jtag device identification register 16 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver the following sections provide a brief description of each instruction. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). extest the required extest instruction places the ic into an external boundary- test mode and selects the boundary-scan register to be connected between tdi and tdo. during this instruction, the boundary-scan register is accessed to drive test data off-chip through the boundary outputs, and recieve test data off-chip through the boundary inputs. as such, the extest instruction is the workhorse of ieee. std 1149.1, providing for probe-less testing of solder-joint opens/shorts and of logic cluster function. sample/preload the required sample/preload instruction allows the ic to remain in a normal functional mode and selects the boundary-scan register to be connected between tdi and tdo. during this instruction, the boundary-scan register can be accessed via a data scan operation, to take a sample of the functional data entering and leaving the ic. idcode the optional idcode instruction allows the ic to remain in its functional mode and selects the optional device identification register to be connected between tdi and tdo. the device identification register is a 32-bit shift register containing information regarding the ic manufacturer, device type, and version code. accessing the device identification register does not interfere with the operation of the ic. also, access to the device identification register should be immediately available, via a tap data-scan operation, after power- up of the ic or after the tap has been reset using the optional trst pin or by otherwise moving to the test-logic-reset state. progwrite the progwrite instruction is for writing the idt5t9821 configuration data to the device?s volatile programming registers. this instruction selects the programming register path for shifting data from tdi to tdo during data register scanning. the programming register path has 112 registers (14 bytes) between tdi and tdo. the 12 configuration data bytes are scanned in through tdi first, starting with bit 0. after scanning in the last configuration bit, bit 95, sixteen additional bits must be scanned in to place the configuration data in the proper location. the last sixteen registers in the programming path are reserved, read-only registers. progread the progread instruction is for reading out the idt5t9821 configuration data from the device?s volatile programming registers. this instruction selects the programming register path for shifting data from tdi to tdo during data register scanning. the programming register path has 112 registers between tdi and tdo, and the first bit scanned out through tdo will be bit 0 of the configuration data. progsave and progrestore (eeprom operation) the progsave instruction is for copying the idt5t9821 configuration data from the device?s volatile programming registers to the eeprom. this instruction selects the bypass register path for shifting data from tdi to tdo during data register scanning. the progrestore instruction is for loading the idt5t9821 configuration data from the eeprom to the device?s volatile programming registers. this instruction selects the bypass register path for shifting data from tdi to tdo during data register scanning. during the execution of a progsave or progrestore instruction, the idt5t9821 will not accept a new programming instruction (read, write, save, or restore). all non-programming jtag instructions will function properly, but the user should wait until the save or restore is complete before issuing a new programming instruction. the time it takes for the save and restore instructions to complete depends on the pll oscillator frequency, f vco . the restore time, t restore , and the save time, t save , can be calculated as follows: t restore = 1.23x10 6 /f vco (ms) t save = 3.09x10 6 / f vco + 52 (ms) if a new programming instruction is issued before the save or restore completes, the new instruction is ignored, and the bypass register path remains in effect for shifting data from tdi to tdo during data register scanning. in order for the progsave and progrestore instructions to function properly, the idt5t9821 must not be in power-down mode ( pd must be high), and the pll must be enabled ( pll_en = low and bit 57 = 0). on power-up of the idt5t9821, an automatic restore is performed to load the eeprom contents into the internal programming registers. the auto- restore will not function properly if the device is in power-down mode ( pd must be high). the device's auto-restore feature will function regardless of the state of the pll_en pin or bit 57. the time it takes for the device to complete the auto-restore is approximately 3ms. clamp the optional clamp instruction loads the contents from the boundary-scan register onto the outputs of the ic, and selects the one-bit bypass register to be connected between tdi and tdo. during this instruction, data can be shifted through the bypass register from tdi to tdo without affecting the condition of the ic outputs. high-impedance the optional high-impedance instruction sets all outputs (including two-state as well as three-state types) of an ic to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between tdi and tdo. during this instruction, data can be shifted through the bypass register from tdi to tdo without affecting the condition of the ic outputs. bypass the required bypass instruction allows the ic to remain in a normal functional mode and selects the one-bit bypass register to be connected between tdi and tdo. the bypass instruction allows serial data to be transferred through the ic from tdi to tdo without affecting the operation of the ic. 17 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver jtag ac electrical characteristics symbol parameter min. max. units t tclk jtag clock input period 100 ? ns t tclkhigh jtag clock high 40 ? ns t tclklow jtag clock low 40 ? ns t tclkrise jtag clock rise time ? 5 (1) ns t tclkfall jtag clock fall time ? 5 (1) ns t rst jtag reset 50 ? ns t rsr jtag reset recovery 50 ? ns note: 1. guaranteed by design. standard jtag timing note: t1 = t tclklow t2 = t tclkhigh t3 = t tclkfall t4 = t tclkrise t5 = t rst (reset pulse width) t6 = t rsr (reset recovery) tclk tdi/tms tdo trst t tclk t1 t2 t3 t4 t5 t6 t ds t dh t do tdo system interface parameters symbol parameter min. max. units t do data output (1) ?20ns t doh data output hold (1) 0?ns t ds data input, t rise = 3ns 10 ? ns t dh data input, t fall = 3ns 10 ? ns note: 1. 50pf loading on external output signals. programming notes once the idt5t9821 has been programmed either with a progwrite or progrestore instruction, the device will attempt to achieve p hase lock using the new pll configuration. if there is a valif ref and fb input clock connected to the device, and it does not achieve lock, the user should issue a progread instruction to confirm that the pll configuration data is valid. on power-up and before the automatic progrestore instruction has completed, the internal programming registers will contain the value of '0' for all bits 95:0. the pll will remain at the minimum frequency and will not achieve phase lock until after the automatic restore is completed. i f the outputs are enabled by the nsoe pins, the outputs will toggle at the minimum frequency. if the outputs are disabled by the nsoe pins, and the omode pin is set high, the nq[1:0] and qfb are stopped high, while qfb is stopped low. 18 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver note: 1. these inputs are normally wired to v dd , gnd, or left floating. internal termination resistors bias unconnected inputs to v dd /2. if these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and the pll may require additional t lock time before all datasheet limits are achieved. dc electrical characteristics over operating range symbol parameter test conditions min. max unit v ihh input high voltage level (1) 3-level inputs only v dd ? 0.4 ? v v imm input mid voltage level (1) 3-level inputs only v dd /2 ? 0.2 v dd /2 + 0.2 v v ill input low voltage level (1) 3-level inputs only ? 0.4 v v in = v dd high level ? 200 i 3 3-level input dc current v in = v dd /2 mid level ?50 +50 a (addr0, addr1) v in = gnd low level ?200 ? i pu input pull-up current v dd = max., v in = gnd ?100 ? a 19 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver dc electrical characteristics over operating range for hstl (1) symbol parameter test conditions min. typ. (7) max unit input characteristics i ih input high current v dd = 2.7v v i = v ddqn /gnd ? ? 5 a i il input low current v dd = 2.7v v i = gnd/v ddqn ??5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 +3.6 v v dif dc differential voltage (2,8) 0.2 ? v v cm dc common mode input voltage (3,8) 680 750 900 mv v ih dc input high (4,5,8) v ref + 100 ? mv v il dc input low (4,6,8) ?v ref - 100 mv v ref single-ended reference voltage (4,8) ? 750 ? mv output characteristics v oh output high voltage i oh = -8ma v ddqn - 0.4 ? v i oh = -100 av ddqn - 0.1 ? v ol output low voltage i ol = 8ma ? 0.4 v i ol = 100 a ? 0.1 v ox nq/ nq and fb/ fb output crossing point v ddqn /2 - 150 v ddqn /2 v ddqn /2 + 150 mv notes: 1. see recommended operating range table. 2. v dif specifies the minimum input differential voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. differential mode only. the dc differential voltage must be maintained to guarantee retaining the existing high or low input. the ac differenti al voltage must be achieved to guarantee switching to a new state. 3. v cm specifies the maximum allowable range of (v tr + v cp ) /2. differential mode only. 4. for single-ended operation, in differential mode, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . 5. voltage required to maintain a logic high, single-ended operation in differential mode. 6. voltage required to maintain a logic low, single-ended operation in differential mode. 7. typical values are at v dd = 2.5v, v ddqn = 1.5v, +25c ambient. 8. the reference clock input is capable of hstl, ehstl, lvepecl, 1.8v or 2.5v lvttl operation independent of the device output. (see input/output selection table.) notes: 1. these power consumption characteristics are for all the valid input interfaces and cover the worst case input and output inte rface combinations. 2. the termination resistors are excluded from these measurements. 3. if the differential input interface is used, the true input is held low and the complementary input is held high. 4. bit 60 = 1. 5. all outputs are at the same interface level. power supply characteristics for hstl outputs (1) symbol parameter test conditions (2) typ. max unit i ddq quiescent v dd power supply current (3) v ddqn = max., ref = low, pd = high, nsoe = low, 112 150 ma pll_en = high, outputs enabled, all outputs unloaded i ddqq quiescent v ddqn power supply current (3) v ddqn = max., ref = low, pd = high, nsoe = low, 2 75 a pll_en = high, outputs enabled, all outputs unloaded i ddpd power down current v dd = max., pd = low, nsoe = low, pll_en = high 0.3 3 ma i ddd dynamic v dd power supply v dd = max., v ddqn = max., c l = 0pf 22 30 a/mhz current per output i dddq dynamic v ddqn power supply v dd = max., v ddqn = max., c l = 0pf 19 30 a/mhz current per output i tot total power v dd supply current (4,5) v ddqn = 1.5v, f vco = 100mhz, c l = 15pf 280 400 ma v ddqn = 1.5v, f vco = 250mhz, c l = 15pf 320 450 i totq total power v ddqn supply current (4,5) v ddqn = 1.5v, f vco = 100mhz, c l = 15pf 130 200 ma v ddqn = 1.5v, f vco = 250mhz, c l = 15pf 220 330 20 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver differential input ac test conditions for hstl symbol parameter value units v dif input signal swing (1) 1v v x differential input signal crossing point (2) 750 mv v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 1 v/ns notes: 1. the 1v peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (at e) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 750mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) envir onment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 1v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. dc electrical characteristics over operating range for ehstl (1) symbol parameter test conditions min. typ. (7) max unit input characteristics i ih input high current v dd = 2.7v v i = v ddqn /gnd ? ? 5 a i il input low current v dd = 2.7v v i = gnd/v ddqn ??5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 +3.6 v v dif dc differential voltage (2,8) 0.2 ? v v cm dc common mode input voltage (3,8) 800 900 1000 mv v ih dc input high (4,5,8) v ref + 100 ? mv v il dc input low (4,6,8) ?v ref - 100 mv v ref single-ended reference voltage (4,8) ? 900 ? mv output characteristics v oh output high voltage i oh = -8ma v ddqn - 0.4 ? v i oh = -100 av ddqn - 0.1 ? v v ol output low voltage i ol = 8ma ? 0.4 v i ol = 100 a ? 0.1 v v ox nq/ nq and fb/ fb output crossing point v ddqn /2 - 150 v ddqn /2 v ddqn /2 + 150 mv notes: 1. see recommended operating range table. 2. v dif specifies the minimum input differential voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. differential mode only. the dc differential voltage must be maintained to guarantee retaining the existing high or low input. the ac differenti al voltage must be achieved to guarantee switching to a new state. 3. v cm specifies the maximum allowable range of (v tr + v cp ) /2. differential mode only. 4. for single-ended operation, in a differential mode, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . 5. voltage required to maintain a logic high, single-ended operation in differential mode. 6. voltage required to maintain a logic low, single-ended operation in differential mode. 7. typical values are at v dd = 2.5v, v ddqn = 1.8v, +25c ambient. 8. the reference clock input is capable of hstl, ehstl, lvepecl, 1.8v or 2.5v lvttl operation independent of the device output. (see input/output selection table.) 21 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver differential input ac test conditions for ehstl symbol parameter value units v dif input signal swing (1) 1v v x differential input signal crossing point (2) 900 mv v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 1 v/ns notes: 1. the 1v peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (at e) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 900mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) envir onment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 1v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. notes: 1. these power consumption characteristics are for all the valid input interfaces and cover the worst case input and output inte rface combinations. 2. the termination resistors are excluded from these measurements. 3. if the differential input interface is used, the true input is held low and the complementary input is held high. 4. bit 60 = 1. 5. all outputs are at the same interface level. power supply characteristics for ehstl outputs (1) symbol parameter test conditions (2) typ. max unit i ddq quiescent v dd power supply current (3) v ddqn = max., ref = low, pd = high, nsoe = low, 112 150 ma pll_en = high, outputs enabled, all outputs unloaded i ddqq quiescent v ddqn power supply current (3) v ddqn = max., ref = low, pd = high, nsoe = low, 2 75 a pll_en = high, outputs enabled, all outputs unloaded i ddpd power down current v dd = max., pd = low, nsoe = low, pll_en = high 0.3 3 ma i ddd dynamic v dd power supply v dd = max., v ddqn = max., c l = 0pf 22 30 a/mhz current per output i dddq dynamic v ddqn power supply v dd = max., v ddqn = max., c l = 0pf 22 30 a/mhz current per output i tot total power v dd supply current (4,5) v ddqn = 1.8v, f vco = 100mhz, c l = 15pf 280 400 ma v ddqn = 1.8v, f vco = 250mhz, c l = 15pf 330 450 i totq total power v ddqn supply current (4,5) v ddqn = 1.8v, f vco = 100mhz, c l = 15pf 160 250 ma v ddqn = 1.8v, f vco = 250mhz, c l = 15pf 270 400 22 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver dc electrical characteristics over operating range for lvepecl (1) symbol parameter test conditions min. typ. (2) max unit input characteristics i ih input high current v dd = 2.7v v i = v ddqn /gnd ? ? 5 a i il input low current v dd = 2.7v v i = gnd/v ddqn ??5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 ? 3.6 v v cm dc common mode input voltage (3,5) 915 1082 1248 mv v ref single-ended reference voltage (4,5) ? 1082 ? mv v ih dc input high 1275 ? 1620 mv v il dc input low 555 ? 875 mv notes: 1. see recommended operating range table. 2. typical values are at v dd = 2.5v, +25c ambient. 3. v cm specifies the maximum allowable range of (v tr + v cp ) /2. differential mode only. 4. for single-ended operation while in differential mode, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . 5. the reference clock input is capable of hstl, ehstl, lvepecl, 1.8v or 2.5v lvttl operation independent of the device output. (see input/output selection table.) differential input ac test conditions for lvepecl symbol parameter value units v dif input signal swing (1) 732 mv v x differential input signal crossing point (2) 1082 mv v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 1 v/ns notes: 1. the 732mv peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 1082mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) envi ronment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 1v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. 23 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver notes: 1. see recommended operating range table. 2. for 2.5v lvttl single-ended operation, bits 35/34, 33/32, 31/30 = 0/1 or 1/0, and ref [1:0] /v ref [1:0] is left floating. if bits 47 - 36 = 0, fb /v ref 2 should be left floating. 3. v dif specifies the minimum input differential voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. differential mode only. the dc differential voltage must be maintained to guarantee retaining the existing high or low input. the ac differenti al voltage must be achieved to guarantee switching to a new state. 4. v cm specifies the maximum allowable range of (v tr + v cp ) /2. differential mode only. 5. for single-ended operation, in differential mode, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . 6. voltage required to maintain a logic high, single-ended operation in differential mode. 7. voltage required to maintain a logic low, single-ended operation in differential mode. 8. typical values are at v dd = 2.5v, v ddqn = v dd , +25c ambient. 9. the reference clock input is capable of hstl, ehstl, lvepecl, 1.8v or 2.5v lvttl operation independent of the device output. (see input/output selection table.) dc electrical characteristics over operating range for 2.5v lvttl (1) symbol parameter test conditions min. typ. (8) max unit input characteristics i ih input high current v dd = 2.7v v i = v ddqn /gnd ? ? 5 a i il input low current v dd = 2.7v v i = gnd/v ddqn ??5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 +3.6 v single-ended inputs (2) v ih dc input high 1.7 ? v v il dc input low ? 0.7 v differential inputs v dif dc differential voltage (3,9) 0.2 ? v v cm dc common mode input voltage (4,9) 1150 1250 1350 mv v ih dc input high (5,6,9) v ref + 100 ? mv v il dc input low (5,7,9) ?v ref - 100 mv v ref single-ended reference voltage (5,9) ? 1250 ? mv output characteristics v oh output high voltage i oh = -12ma v ddqn - 0.4 ? v i oh = -100 av ddqn - 0.1 ? v v ol output low voltage i ol = 12ma ? 0.4 v i ol = 100 a ? 0.1 v 24 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver single-ended input ac test conditions for 2.5v lvttl symbol parameter value units v ih input high voltage v dd v v il input low voltage 0v v thi input timing measurement reference level (1) v dd /2 v t r , t f input signal edge rate (2) 2 v/ns notes: 1. a nominal 1.25v timing measurement reference level is specified to allow constant, repeatable results in an automatic test eq uipment (ate) environment. 2. the input signal edge rate of 2v/ns or greater is to be maintained in the 10% to 90% range of the input waveform. differential input ac test conditions for 2.5v lvttl symbol parameter value units v dif input signal swing (1) v dd v v x differential input signal crossing point (2) v dd /2 v v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 2.5 v/ns notes: 1. a nominal 2.5v peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equip ment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a nominal 1.25v crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate ) environment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 2.5v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. notes: 1. these power consumption characteristics are for all the valid input interfaces and cover the worst case input and output inte rface combinations. 2. the termination resistors are excluded from these measurements. 3. if the differential input interface is used, the true input is held low and the complementary input is held high. 4. bit 60 = 1. 5. all outputs are at the same interface level. power supply characteristics for 2.5v lvttl outputs (1) symbol parameter test conditions (2) typ. max unit i ddq quiescent v dd power supply current (3) v ddqn = max., ref = low, pd = high, nsoe = low, 112 150 ma pll_en = high, outputs enabled, all outputs unloaded i ddqq quiescent v ddqn power supply current (3) v ddqn = max., ref = low, pd = high, nsoe = low, 15 75 a pll_en = high, outputs enabled, all outputs unloaded i ddpd power down current v dd = max., pd = low, nsoe = low, pll_en = high 0.3 3 ma i ddd dynamic v dd power supply v dd = max., v ddqn = max., c l = 0pf 21 30 a/mhz current per output i dddq dynamic v ddqn power supply v dd = max., v ddqn = max., c l = 0pf 33 40 a/mhz current per output i tot total power v dd supply current (4,5) v ddqn = 2.5v., f vco = 100mhz, c l = 15pf 280 400 ma v ddqn = 2.5v., f vco = 250mhz, c l = 15pf 320 450 i totq total power v ddqn supply current (4,5) v ddqn = 2.5v., f vco = 100mhz, c l = 15pf 210 320 ma v ddqn = 2.5v., f vco = 250mhz, c l = 15pf 345 530 25 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver notes: 1. see recommended operating range table. 2. for 1.8v lvttl single-ended operation, bits 35 - 30 = 0 and ref [1:0] /v ref [1:0] is left floating. if bits 47/46, 45/44, 43/42, 41/40, 39/38, 37/36 = 0/1, fb /v ref 2 should be left floating. 3. v dif specifies the minimum input differential voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. differential mode only. the dc differential voltage must be maintained to guarantee retaining the existing high or low input. the ac differenti al voltage must be achieved to guarantee switching to a new state. 4. v cm specifies the maximum allowable range of (v tr + v cp ) /2. differential mode only. 5. for single-ended operation in differential mode, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . the input is guaranteed to toggle within 200mv of v ref [1:0] when v ref [1:0] is constrained within +600mv and v ddi -600mv, where v ddi is the nominal 1.8v power supply of the device driving the ref [1:0] input. to guarantee switching in voltage range specified in the jedec 1.8v lvttl interface specification, v ref [1:0] must be maintained at 900mv with appropriate tolerances. 6. voltage required to maintain a logic high, single-ended operation in differential mode. 7. voltage required to maintain a logic low, single-ended operation in differential mode. 8. typical values are at v dd = 2.5v, v ddqn = 1.8v, +25c ambient. 9. the reference clock input is capable of hstl, ehstl, lvepecl, 1.8v or 2.5v lvttl operation independent of the device output. (see input/output selection table.) 10. this value is the worst case minimum v ih over the specification range of the 1.8v power supply. the 1.8v lvttl specification is v ih = 0.65 * v dd where v dd is 1.8v 0.15v. however, the lvttl translator is supplied by a 2.5v nominal supply on this part. to ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( v ih = 0.65 * [1.8 - 0.15v]) rather than reference against a nominal 1.8v supply. 11. this value is the worst case maximum v il over the specification range of the 1.8v power supply. the 1.8v lvttl specification is v il = 0.35 * v dd where v dd is 1.8v 0.15v. however, the lvttl translator is supplied by a 2.5v nominal supply on this part. to ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( v il = 0.35 * [1.8 + 0.15v]) rather than reference against a nominal 1.8v supply. dc electrical characteristics over operating range for 1.8v lvttl (1) symbol parameter test conditions min. typ. (8) max unit input characteristics i ih input high current v dd = 2.7v v i = v ddqn /gnd ? ? 5 a i il input low current v dd = 2.7v v i = gnd/v ddqn ??5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 v ddqn + 0.3 v single-ended inputs (2) v ih dc input high 1.073 (10) ?v v il dc input low ? 0.683 (11) v differential inputs v dif dc differential voltage (3,9) 0.2 ? v v cm dc common mode input voltage (4,9) 825 900 975 mv v ih dc input high (5,6,9) v ref + 100 ? mv v il dc input low (5,7,9) ?v ref - 100 mv v ref single-ended reference voltage (5,9) ? 900 ? mv output characteristics v oh output high voltage i oh = -6ma v ddqn - 0.4 ? v i oh = -100 av ddqn - 0.1 ? v v ol output low voltage i ol = 6ma ? 0.4 v i ol = 100 a ? 0.1 v 26 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver single-ended input ac test conditions for 1.8v lvttl symbol parameter value units v ih input high voltage (1) v ddi v v il input low voltage 0v v thi input timing measurement reference level (2) v ddi /2 mv t r , t f input signal edge rate (3) 2 v/ns notes: 1. v ddi is the nominal 1.8v supply (1.8v 0.15v) of the part or source driving the input. 2. a nominal 900mv timing measurement reference level is specified to allow constant, repeatable results in an automatic test eq uipment (ate) environment. 3. the input signal edge rate of 2v/ns or greater is to be maintained in the 10% to 90% range of the input waveform. differential input ac test conditions for 1.8v lvttl symbol parameter value units v dif input signal swing (1) v ddi v v x differential input signal crossing point (2) v ddi /2 mv v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 1.8 v/ns notes: 1. v ddi is the nominal 1.8v supply (1.8v 0.15v) of the part or source driving the input. a nominal 1.8v peak-to-peak input pulse le vel is specified to allow consistent, repeatable results in an automatic test equipment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a nominal 900mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate ) environment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 1.8v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. notes: 1. these power consumption characteristics are for all the valid input interfaces and cover the worst case input and output inte rface combinations. 2. the termination resistors are excluded from these measurements. 3. if the differential input interface is used, the true input is held low and the complementary input is held high. 4. bit 60 = 1. 5. all outputs are at the same interface level. power supply characteristics for 1.8v lvttl outputs (1) symbol parameter test conditions (2) typ. max unit i ddq quiescent v dd power supply current (3) v ddqn = max., ref = low, pd = high, nsoe = low, 112 150 ma pll_en = high, outputs enabled, all outputs unloaded i ddqq quiescent v ddqn power supply current (3) v ddqn = max., ref = low, pd = high, nsoe = low, 2 75 a pll_en = high, outputs enabled, all outputs unloaded i ddpd power down current v dd = max., pd = low, nsoe = low, pll_en = high 0.3 3 ma i ddd dynamic v dd power supply v dd = max., v ddqn = max., c l = 0pf 19 30 a/mhz current per output i dddq dynamic v ddqn power supply v dd = max., v ddqn = max., c l = 0pf 22 30 a/mhz current per output i tot total power v dd supply current (4,5) v ddqn = 1.8v., f vco = 100mhz, c l = 15pf 275 400 ma v ddqn = 1.8v., f vco = 250mhz, c l = 15pf 310 450 i totq total power v ddqn supply current (4,5) v ddqn = 1.8v., f vco = 100mhz, c l = 15pf 135 200 ma v ddqn = 1.8v., f vco = 250mhz, c l = 15pf 200 300 27 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver ac electrical characteristics over operating range all outputs at the same interface level symbol parameter min. typ. max unit f nom vco frequency range see jtag/i 2 c serial configurations: vco frequency range table t rpw reference clock pulse width high or low 1 ? ? ns t fpw feedback input pulse width high or low 1 ? ? ns t sk ( o ) output skew (rise-rise, fall-fall, nominal) (1,2) ? ? 100 ps t sk 1 ( ) multiple frequency skew (rise-rise, fall-fall, nominal-divided, divided-divided) (1,2,3) ? ? 100 ps t sk 2 ( ) multiple frequency skew (rise-fall, nominal-divided, divided-divided) (1,2,3) ? ? 300 ps t sk 1 ( inv ) inverting skew (nominal-inverted) (1,2) ?? 300 ps t sk 2 ( inv ) inverting skew (rise-rise, fall-fall, rise-fall, inverted-divided) (1,2,3) ? ? 300 ps t sk ( pr ) process skew (1,2,4) ?? 300 ps t( ) ref input to fb static phase offset (5) -100 ? 100 ps t odcv output duty cycle variation from 50% (11,12) 1.8v lvttl -375 ? 375 ps 2.5v lvttl -275 ? 275 t orise output rise time (6) hstl / ehstl / 1.8v lvttl ? ? 1.2 ns 2.5v lvttl ? ? 1 t ofall output fall time (6) hstl / ehstl / 1.8v lvttl ? ? 1.2 ns 2.5v lvttl ? ? 1 t l power-up pll lock time (7) ?? 4ms t l ( ) pll lock time after input frequency change (7) ?? 1ms t l ( pd ) pll lock time after asserting pd pin (7) ?? 1ms t l ( refsel 1 ) pll lock time after change in ref_sel (7,9) ? ? 100 s t l ( refsel 2 ) pll lock time after change in ref_sel (ref 1 and ref 0 are different frequency) (7) ?? 1ms t jit ( cc ) cycle-to-cycle output jitter (peak-to-peak) (2,8) ? 50 75 ps t jit ( per ) period jitter (peak-to-peak) (2,8) ?? 75 ps t jit ( hp ) half period jitter (peak-to-peak) (2,8,10) ?? 125 ps t jit ( duty ) duty cycle jitter (peak-to-peak) (2,8) ?? 100 ps v ox hstl and ehstl differential true and complementary output crossing voltage level v ddqn /2 - 150 v ddqn /2 v ddqn /2 + 150 mv notes: 1. skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the spe cified load. 2. for differential lvttl outputs, the measurement is made at v ddqn /2, where the true outputs are only compared with other true outputs and the complementary outputs are only compared to other complementary outputs. for differential hstl/ehstl outputs, the measurement is made at the crossing point ( v ox ) of the true and complementary signals. 3. there are three classes of outputs: nominal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode). 4. t sk ( pr ) is the output to corresponding output skew between any two devices operating under the same conditions (v dd and v ddqn , ambient temperature, air flow, etc.). 5. t( ) is measured with ref and fb the same type of input, the same rise and fall times. for 1.8v / 2.5v lvttl input and output, th e measurement is taken from v thi on ref to v thi on fb. for hstl / ehstl input and output, the measurement is taken from the crosspoint of ref/ ref to the crosspoint of fb/ fb . all outputs are set to zero delay, fb input divider is set to divide-by-one, and bit 60 = 1. 6. output rise and fall times are measured between 20% to 80% of the actual output voltage swing. 7. t l , t l ( ), t l ( refsel 1 ), t l ( refsel 2 ), and t l ( pd ) are the times that are required before the synchronization is achieved. these specifications are valid only after v dd /v ddqn is stable and within the normal operating limits. these parameters are measured from the application of a new signal at ref or fb, or after pd is (re)asserted until t( ) is within specified limits. 8. the jitter parameters are measured with all outputs selected for zero delay, fb input divider is set to divide-by-one, and bi t 60 = 1. 9. both ref inputs must be the same frequency, but up to 180 out of phase. 10. for hstl/ehstl outputs only. 11. for lvttl outputs only. 12. t odcv is measured with all outputs selected for zero delay. 28 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver ac electrical characteristics over operating range all outputs at the different interface level symbol parameter min. typ. max unit f nom vco frequency range see jtag/i 2 c serial configurations: vco frequency range table t rpw reference clock pulse width high or low 1 ? ? ns t fpw feedback input pulse width high or low 1 ? ? ns t sk ( o ) output skew (rise-rise, fall-fall, nominal) (1,2) ? ? 250 ps t sk 1 ( ) multiple frequency skew (rise-rise, fall-fall, nominal-divided, divided-divided) (1,2,3) ? ? 500 ps t sk 2 ( ) multiple frequency skew (rise-fall, nominal-divided, divided-divided) (1,2,3) ? ? 500 ps t sk 1 ( inv ) inverting skew (nominal-inverted) (1,2) ?? 500 ps t sk 2 ( inv ) inverting skew (rise-rise, fall-fall, rise-fall, inverted-divided) (1,2,3) ? ? 500 ps t sk ( pr ) process skew (1,2,4) ?? 400 ps t( ) ref input to fb static phase offset (5) -200 ? 200 ps t odcv output duty cycle variation from 50% (11,12) 1.8v lvttl -475 ? 475 ps 2.5v lvttl -375 ? 375 t orise output rise time (6) hstl / ehstl / 1.8v lvttl ? ? 1.2 ns 2.5v lvttl ? ? 1 t ofall output fall time (6) hstl / ehstl / 1.8v lvttl ? ? 1.2 ns 2.5v lvttl ? ? 1 t l power-up pll lock time (7) ?? 4ms t l ( ) pll lock time after input frequency change (7) ?? 1ms t l ( pd ) pll lock time after asserting pd pin (7) ?? 1ms t l ( refsel 1 ) pll lock time after change in ref_sel (7,9) ? ? 100 s t l ( refsel 2 ) pll lock time after change in ref_sel (ref 1 and ref 0 are different frequency) (7) ?? 1ms t jit ( cc ) cycle-to-cycle output jitter (peak-to-peak) (2,8) ? ? 100 ps t jit ( per ) period jitter (peak-to-peak) (2,8) ?? 100 ps t jit ( hp ) half period jitter (peak-to-peak) (2,8,10) ?? 200 ps t jit ( duty ) duty cycle jitter (peak-to-peak) (2,8) ?? 150 ps v ox hstl and ehstl differential true and complementary output crossing voltage level v ddqn /2 - 150 v ddqn /2 v ddqn /2 + 150 mv notes: 1. skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the spe cified load. 2. for differential lvttl outputs, the measurement is made at v ddqn /2, where the true outputs are only compared with other true outputs and the complementary outputs are only compared to other complementary outputs. for differential hstl/ehstl outputs, the measurement is made at the crossing point ( v ox ) of the true and complementary signals. 3. there are three classes of outputs: nominal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode). 4. t sk ( pr ) is the output to corresponding output skew between any two devices operating under the same conditions (v dd and v ddqn , ambient temperature, air flow, etc.). 5. t( ) is measured with ref and fb the same type of input, the same rise and fall times. for 1.8v / 2.5v lvttl input and output, th e measurement is taken from v thi on ref to v thi on fb. for hstl / ehstl input and output, the measurement is taken from the crosspoint of ref/ ref to the crosspoint of fb/ fb . all outputs are set to zero delay, fb input divider is set to divide-by-one, and bit 60 = 1. 6. output rise and fall times are measured between 20% to 80% of the actual output voltage swing. 7. t l , t l ( ), t l ( refsel 1 ), t l ( refsel 2 ), and t l ( pd ) are the times that are required before the synchronization is achieved. these specifications are valid only after v dd /v ddqn is stable and within the normal operating limits. these parameters are measured from the application of a new signal at ref or fb, or after pd is (re)asserted until t( ) is within specified limits. 8. the jitter parameters are measured with all outputs selected for zero delay, fb input divider is set to divide-by-one, and bi t 60 = 1. 9. both ref inputs must be the same frequency, but up to 180 out of phase. 10. for hstl/ehstl outputs only. 11. for lvttl outputs only. 12. t odcv is measured with all outputs selected for zero delay. 29 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver ac differential input specifications (1) symbol parameter min. typ. max unit t w reference/feedback input clock pulse width high or low (hstl/ehstl outputs) (2) 1??ns reference/feedback input clock pulse width high or low (2.5v / 1.8v lvttl outputs) (2) 1?? hstl/ehstl/1.8v lvttl/2.5v lvttl v dif ac differential voltage (3) 400 ? ? mv v ih ac input high (4,5) vx + 200 ? ? mv v il ac input low (4,6) ? ? vx - 200 mv lvepecl v dif ac differential voltage (3) 400 ? ? mv v ih ac input high (4) 1275 ? ? mv v il ac input low (4) ? ? 875 mv notes: 1. for differential input mode, bits 35 - 30 = 1. 2. both differential input signals should not be driven to the same level simultaneously. the input will not change state until the inputs have crossed and the voltage range defined by v dif has been met or exceeded. 3. differential mode only. v dif specifies the minimum input voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. the ac differential voltage must be achieved to guarantee switching to a new state. 4. for single-ended operation, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . refer to each input interface's dc specification for the correct v ref [1:0] range. 5. voltage required to switch to a logic high, single-ended operation only. 6. voltage required to switch to a logic low, single-ended operation only. 30 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver ac timing diagram (1) ref fb q other q inverted q q divided by 2 q divided by 4 ref fb q other q inverted q q divided by 2 q divided by 4 t fpwh t fpwl t rpwh t rpwl t sk1(inv) t sk2( ), t sk2(inv) t sk1( ), t sk2(inv) t sk1( ) t sk2( ) t sk2(inv) t sk1(inv) t sk(o) t sk(o) t odcv t odcv note: 1. the ac timing diagram applies to bit 58 = 1. for bit 58 = 0, the negative edge of fb aligns with the negative edge of ref [1:0] , divided outputs change on the negative edge of ref [1:0] , and the positive edges of the divide-by-2 and divide-by-4 signals align. 31 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver duty-cycle jitter nq, q fb nq, q fb t w(min) t w(max) t jit(duty) = t w(max) - t w(min) jitter and offset timing waveforms nq, q fb t cycle n t cycle n + 1 nq, q fb t jit(cc) t cycle n t cycle n+1 = cycle-to-cycle jitter static phase offset fb ref [1:0] t (?)n ref [1:0] fb t (?)n + 1 t (?) = n n = n 1 t (?)n (n is a large number of samples) note: 1. diagram for bit 58 = 1 and hstl / ehstl input and output. 32 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver period jitter t jit(per) = t cycle n 1 f o nq, q fb nq, q fb t cycle n 1 f o nq, q fb nq, q fb 1 f o t jit(hper) = t half period n 1 2*f o t half period n t half period n+1 nq, q fb nq, q fb nq, q fb nq, q fb half-period jitter note: 1. 1/fo = average period. note: 1. 1/fo = average period. 33 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver test circuits and conditions test circuit for differential input (1) v dd v ddqn d.u.t. ref [1:0] ref [1:0] pulse generator 3 inch, ~50 ? transmission line 3 inch, ~50 ? transmission line v in v in v ddi r1 r2 v ddi r1 r2 differential input test conditions symbol v dd = 2.5v 0.2v unit r1 100 ? r2 100 ? v ddi v cm *2 v hstl: crossing of ref [1:0] and ref [1:0] ehstl: crossing of ref [1:0] and ref [1:0] v thi lvepecl: crossing of ref [1:0] and ref [1:0] v 1.8v lvttl: v ddi /2 2.5v lvttl: v dd /2 note: 1. this input configuration is used for all input interfaces. for single-ended testing, the ref [1:0] must be left floating. for testing single-ended in differential input mode, the v in should be floating. 34 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver v dd v ddqn d.u.t. q fb q fb c l v ddqn r1 r2 v ddqn r1 r2 c l ref [1:0] fb fb sw1 test circuit for outputs test circuit for differential feedback differential feedback test conditions symbol v dd = 2.5v 0.2v unit v ddqn = interface specified c l 15 pf r1 100 ? r2 100 ? v ox hstl: crossing of q fb and q fb v ehstl: crossing of q fb and q fb v tho 1.8v lvttl: v ddqn /2 v 2.5v lvttl: v ddqn /2 sw1 1.8v/2.5v lvttl open hstl/ehstl closed v dd v ddqn d.u.t. c l v ddqn r1 r2 nq fb fb qfb qfb ref [1:0] nq c l v ddqn r1 r2 sw1 differential output test conditions symbol v dd = 2.5v 0.2v unit v ddqn = interface specified c l 15 pf r1 100 ? r2 100 ? v ox hstl: crossing of nq and nq v ehstl: crossing of nq and nq v tho 1.8v lvttl: v ddqn /2 v 2.5v lvttl: v ddqn /2 sw1 1.8v/2.5v lvttl open hstl/ehstl closed 35 industrial temperature range idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver ordering information idt xxxxx xx package device type 5t9821 eeprom programmable 2.5v zero delay pll differential cloc k driver thermally enhanced plastic very fine pitch quad flat no lead package nl package x -40c to +85c (industrial) i corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com |
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